The vector network analyzer (VNA) provides a framework for characterization of microwave properties of materials, semiconductor devices and circuits, transmission lines, and scores of other test subjects. Decades of research and development work have produced a wealth of calibration methods, used to remove the effects of cables, probes, and other portions of the measurement apparatus, leaving only the desired device under test (DUT) between the reference planes (the demarcation lines separating calibrated measurement apparatus from measurement subject). However, in many cases, it is not practical to arrange that the entirety of unwanted effects is removed using these calibration procedures. In these cases, calibration is often followed by de-embedding—a procedure which moves the calibration reference planes closer together, moving portions of what otherwise would be the DUT outside of the reference planes.
High frequency on-wafer measurements of single transistors, simple circuits, and transmission line structures are critical to characterization and development of advanced integrated circuit technologies. Although there exist many possible calibration and de-embedding methods, each has its drawbacks. Although on-wafer calibrations may be performed (TRL, LRM, LRRM, etc.), these require a number of precisely designed, fabricated, and verified calibration structures which consume significant amounts of expensive wafer real estate and which may not be trivial to reproduce at the desired level of precision, particularly in advanced and emerging integrated circuit processes in which process steps may be intentionally (or unintentionally) varied in order to explore design space.
Off-wafer calibrations do not suffer from the same constraints, but introduce other difficulties. For example, differences in the probing environment between the calibration substrate and the measurement substrate (e.g., substrate dielectric constant, substrate thickness, etc.) lead to ambiguity in the calibration reference plane. Perhaps most importantly (particularly for single transistor measurements) the effects of the on-wafer probe pads and traces leading to the desired device under test (DUT) can overwhelm the DUT response. A wealth of de-embedding techniques can be used to solve these issues, pushing the effective reference planes defined by an off-wafer calibration to some on-wafer location, but these, too, have limitations. The most widely used techniques for transistor measurement involve open (Y) and/or short (Z) subtraction, which have been proven quite useful at lower frequencies, but which are limited in use at higher frequencies because, although the mathematics and matrix formulations are by nature distributed, the common Y and Z subtraction methods treat shunt and series components separately and hence amount to lumped element subtractions of capacitive and inductive parasitics. Although in principal, this lumped element limitation can be mitigated by reducing the dimensions of the probe pads and lead-in traces, as the measurement frequencies increase, decreasing the probe-probe spacing leads to excessive probe-probe coupling which can significantly negatively impact the measurements.
Other de-embedding techniques which do not suffer from the same lumped element constraints as the Y and Z subtraction techniques have been developed. However, these techniques generally require several precisely fabricated structures and/or they make assumptions regarding the network to be de-embedded which may be difficult to ensure. Therefore, implementation of these de-embedding techniques (e.g. for on-wafer measurement) can prove equally difficult to implement as calibration techniques which could supplant the de-embedding procedure (e.g. fabrication of on-wafer calibration structures), or which are limited to the same range of applicability as other methods (e.g. the lumped element approximation implicit in Y and Z subtraction methods).